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Japan / US · Chips & Networking

Chip Testing & Burn-in

Bigger dies, more chiplets and HBM stacks multiply test time. SoC and memory testers become a quiet throughput gate for every accelerator shipped.

Wafer probe→Final test→Burn-in→Ship
70
Tightness score ⓘ
#22 of 56
▲ Tightening
Supply concentration4
Lead time3
Capex intensity3
Geopolitical exposure3
Pricing power4
Lead time
6–12 mo
Theme 1M
−29.4%
% in uptrend
20%
Metric to watch

Advantest and Teradyne SoC-test orders, test time per device, and burn-in commentary.

What would prove us wrong

Weakens if tester lead times shorten while accelerator unit volumes rise.

Test theme performance

Equal-weight · rebased 100 · 1Y
Stocks we track

Who controls this bottleneck

Roles, not recommendations. Delayed prices; local currency.

StockRoleListingLast1D1M3MYTDOff 52w highTrendNext earnings
6857.T
Advantest
SoC and memory testers for AI accelerators and HBM TSE
Japan
¥34,860 −5.86% +1.8% +36.9% +78.0% −16.7% 2027-01-27
TER
Teradyne
SoC test plus Universal Robots cobots NASDAQ
US
$274.4 −7.38% −34.0% −25.0% +41.9% −43.3% 2027-01-27
FORM
FormFactor
Probe cards incl. HBM wafer probe NASDAQ
US
$87.53 −10.19% −41.0% −19.6% +56.9% −45.3% 2026-10-28
AEHR
Aehr Test Systems
Wafer-level burn-in NASDAQ
US
$54.89 −10.33% −46.0% −40.1% +171.9% −62.3% 2026-11-02
COHU
Cohu
Test handlers and interface NASDAQ
US
$50.79 −4.89% −27.8% +4.0% +118.3% −31.3% 2026-10-28